1. Field of the Disclosure
The present invention relates to an electronic circuit comprising a capacitor. In particular the present invention relates to an electronic circuit configured as an (electronic) transceiver of a read/write device for non-contact communication via an electro-magnetic field with at least one data carrier (medium).
2. Related Art
In a communication system, non-contact or wireless communication between a read/write device (reader) and a data carrier (medium) is effected by an electro-magnetic field transceived (modulated, emitted) by the reader, in particular by an electronic transceiver comprising a circuit module, e.g. a communication module or a control module. The electronic transceiver is used for the signal coding, in particular for encoding and decoding of the communication signals or the signals used to provide or carry out the communication. The electronic transceiver comprises at least one capacitor connected to the circuit module. When no communication takes place, the capacitor discharges through the electronic transceiver, or parts of the electronic transceiver such as the circuit module. This is for example the case when the reader, or at least the circuit module, is put into a stop mode or power down mode. Afterwards, the power stabilizing capacitor has to be charged or re-charged before the communication may be resumed, as the capacitor is configured to supply power to the circuit module.
Discharging of a power stabilizing capacitor connected to an electronic circuit is particularly disadvantageous when the energy loss due to charging and discharging of the capacitor is in the same range as the energy (or power) needed to operate the electronic circuit. This is basically not acceptable for a battery operated or battery powered device such as a reader.
The following two patent applications are directed towards different arrangements or circuits for discharge control or discharge prevention.
WO 2008/035523 A1 discloses how to use a MOS-FET, in particular a four-terminal back gate switching MOS-FET, for charge control, but also for discharge control. A back-gate voltage generator circuit, used for generating a back-gate voltage, includes first and second n-type MOS-FETs connected in series through a common source electrode. A voltage at the common source electrode serves as the back-gate voltage of the four-terminal back gate switching MOS-FET, and the back-gate voltage is used as a reference voltage for generating signals for controlling the first and second n-type MOS-FETs.
US 2006/0261751 A1 discloses a discharge prevention circuit and electronic equipment with the discharge prevention circuit. The discharging prevention circuit includes a first power line, a second power line, a capacitor, a current detector, and a switch. The first and second power lines directly or indirectly connect a power feed line to a load. The capacitor and the current detector are directly or indirectly connected in series between the first and second power lines. The switch is disposed in the first or second power line. The current detector detects a charging current to the capacitor and a discharging current from the capacitor. If the current detector detects discharging current from the capacitor, the switch acts to stop current flow between the capacitor and the power feed line.
JP 2000 037036 discloses a power-saving driving circuit which comprises a switching means arranged in a path from a power stabilizing circuit to a distance measuring IC (DMIC). The power-saving driving circuit further comprises a power stabilizing capacitor which has one of its conductors connected to the path between the power stabilizing circuit and the DMIC, and the other conductor connected to ground. When the power stabilizing circuit is turned off, the switching means interrupt the path between the power stabilizing circuit and the DMIC and thereby cut off the power stabilizing capacitor and the power stabilizing circuit from the DMIC. In addition, the power-saving driving circuit comprises a diode which is arranged between the power stabilizing capacitor and the power stabilizing circuit such that the power stabilizing capacitor is also cut off from the power stabilizing circuit when the power stabilizing circuit is turned off. According to JP 2000 037036, the switching means and the diode make it possible to reduce wasteful discharging of the power stabilizing capacitor through the power stabilizing circuit and the DMIC. However, the arrangement of the switching means according to JP 2000 037036 is not suitable in cases where the path between the power stabilizing circuit and the DMIC is not accessible, e.g. if the power stabilizing circuit and the DMIC are part of the same integrated circuit, or in cases where it is not desirable to separate the power stabilizing circuit from the DMIC, e.g. if there are different modes of operation with different levels of power requirements.